1. Field of the Invention
The invention relates to memory, and in particular to programming nonvolatile memory.
2. Description of Related Art
Nonvolatile memory, such as flash, charge trapping, nanocrystal, and programmable resistive memory, is accessed via word lines that apply a gate voltage to each memory cell. During a program operation, the word line voltage must be charged to have a magnitude sufficient to cause charge movement to or from the charge storage structure of the memory cell. When the word line voltage has been charged to a programming voltage, then bit lines corresponding to the memory cells to be programmed cause programming of those memory cells. To perform program verify, the word line voltage is set to the program verify voltage, and the values of the programmed memory cells are verified.
Nonvolatile memory arrays with a long word line with a relatively large capacitance suffer a correspondingly long latency as the word line voltage is charged and discharged to its appropriate program or program verify voltage. In addition to this latency, or word line transient time, the acts of programming and program verifying the memory cells accessed by the word line also take a relatively long time, due to the number of memory cells accessed by the long word line.
Therefore, it would be desirable to decrease the time of programming nonvolatile memory.